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ATJ2001 PDA+MP3 Decoder
Actions Semiconductor Co.,LTD
1. Pin descriptions
Pin No. 1 2 3 4 4(1) 5 5(1) 6 6(1) 7 7(1) 8 8(1) 9 9(1) 10 10(1) 11 11(1) 12 12(1) 13 13(1) 14 14(1) 15 15(1) 16 16(1) 17
3
Pin Name LOSCI LOSCO GND A15 CLE AC'97RSTATA_RSTA16 ALE GIOB0 DAC_BCK A17 ATAD8 GIOB1 DAC_LR A18 ATAD9 GIOB2 DAC_SDATA A19 ATAD10 GIOB3 DAC_FS256 A20 ATAD11 GIOB4 AC'97BITCK A21 ATAD12 GIOB5
I/O Type AI AO PWR O O O O O O BI O O BI BI O O BI BI O O BI BI O O BI BI O O BI BI
Reset Default / / / L L H H L L Z Z L L Z Z L L Z Z L L Z Z L L Z Z L L Z
Short Description Low frequency crystal OSC input Low frequency crystal OSC output Digital signal ground Bit15 of ext. memory address bus Command latch enable of Nand type flash Reset to AC'97 block ATA device reset Bit16 of ext. memory address bus Address latch enable of Nand type flash Bit0 of general purpose I/O port B Ext. DAC bit clock output
Bit17 of ext. memory address bus Bit8 of ATA device data bus Bit1 of general purpose I/O port B Ext. DAC left/right channel output
Bit18 of ext. memory address bus Bit9 of ATA device data bus Bit2 of general purpose I/O port B Ext. DAC serial data output
Bit19 of ext. memory address bus Bit10 of ATA device data bus Bit3 of general purpose I/O port B Ext. DAC 256x over sampling clock
Bit20 of ext. memory address bus Bit11 of ATA device data bus Bit4 of general purpose I/O port B AC'97 codec bit clock Bit21 of ext. memory address bus Bit12 of ATA device data bus Bit5 of general purpose I/O port B
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ATJ2001 PDA+MP3 Decoder
Actions Semiconductor Co.,LTD 17(1) AC'97SYNC O 18 18(1) 19 19(1) 19(2) 20 20(1) 21 21(1) 22 22(1) 22(2) 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 A22 ATAD13 GIOB6 AC'97SDI DAC3LO A23 ATAD14 A24 ATAD15 GIOB7 AC'97SDO DAC3RO VCC USBDUSBD+ USBVBUS PVDD PAOR PAOL PGND PAIR PAIL AOUTR AOUTL VRDA VLAD VRAD AGCI MICOUT MICIN VMIC O BI BI I O O BI O BI BI O O PWR A A I A A A PWR A A A A A A A A A A A / / L / / / / / / / / / / / / / / / Z L L Z Z Z L L L L Z Z Z AC'97 codec sample SYNC Bit22 of ext. memory address bus Bit13 of ATA device data bus Bit6 of general purpose I/O port B AC'97 codec serial data input Int. DAC3 right channel digital output
Bit23 of ext. memory address bus Bit14 of ATA device data bus Bit24 of ext. memory address bus Bit15 of ATA device data bus Bit7 of general purpose I/O port B AC'97 codec serial data output Int. DAC3 right channel digital output
Power supply for Pads circuits (3.15v) USB negative connect USB positive connect USB cable power signal Bypass capacitor for power amplifier Output of right channel power amplifier Output of left channel power amplifier
Ground for power amplifier circuits Input of right channel power amplifier Input of left channel power amplifier
Int. sigma-dalta DAC right channel analog output Int. sigma-dalta DAC left channel analog output Reference voltage for DAC Low voltage for Touch Panel Reference voltage for ADC Microphone ADC amplifier input Microphone pre-amplifier output Microphone pre-amplifier input Power supply for microphone & Touch Panel
4
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Actions Semiconductor Co.,LTD 42 AGND PWR 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 Y2 Y1 X1 X2 AVCC BATSEL IBIAS VREFI VL0 VL1 VL2 VL3 DCDIS VBAT DCF3 DCF2 DCF1 VP1 VDD VP2 DCOP2 DCOP3 DCOP1 AVDD AVSS HOSCI HOSCO GND AI AI AI AI PWR I I A AI AI AI AI I I AI AI AI PWR PWR AI AO AO AO PWR PWR AI AO PWR / / / / / / / / / / / L / / / / / Analog ground for record, touch panel and ADC blocks Connect to touch panel Y2 Connect to touch panel Y1 Connect to touch panel X1 Connect to touch panel X2 Power supply for record, touch panel and ADC blocks (3.15v) Battery select, 0:one battery 1:two batteries Int. bias pin with a ext.R(1.5Mohm) to ground Reference voltage input (1.5v) Battery monitor reference voltage input (1.40v) Battery monitor reference voltage input (1.30v) Battery monitor reference voltage input (1.15v) Battery monitor reference voltage input (1.05v) Int DC-DC convertor disable, 0:enable 1:disable Battery signal input (1.0-1.5v) The third DC-DC feedback pin VCC(3.15V) DC-DC feedback pin VDD(2.35V) DC-DC feedback pin Power supply for int. regulator Power supply for core (2.35v) Input for int. power switch VCC(3.15V) DC-DC pulse output The third DC-DC pulse output VDD(2.35V) DC-DC pulse output Power supply for PLL analog circuits (2.35v) Ground for PLL analog circuits High frequency crystal OSC input High frequency crystal OSC output Digital signal ground
5
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Actions Semiconductor Co.,LTD 71 CKOUT2 O 72 72(1) 73 73(1) 74 74(1) 75 75(1) 76 77 77(1) 77(2) 78 79 79(1) 79(2) 80 80(1) 80(2) 81 81(1) 81(2) 82 82(1) 82(2) 83 83(1) 83(2) 84 85 85(1) 85(2) 86
6
L Z Z H H Z Z Z Z
High frequency clock output Bit0 of general purpose I/O port C UART1 serial input TCP LCM XSCLK output TCP2 LCD module CK Bit1 of general purpose I/O port C UART1 serial output TCP LCM display off control output FM radio IF counter input Power supply for core (2.35v)
GIOC0 SIN1 XSCLK LCDCK GIOC1 SOUT1 DISPOFF FMIFIN VDD FRAME V2 LCM_CE VCC YSCLK_LP LCM_RWLCDCE GIOC2 SIN2 IRRX YDU V1 LCM_CSGIOC3 SOUT2 IRTX GIOF7 SEG19 KEYO7 GIOC4 GIOF6 SEG18 KEYO6 GIOC5
BI I O O BI O O I PWR O O O PWR O O O BI I I O O O BI O O BI O O BI BI O O BI
Z Z Z
TCP LCM frame signal output Int. 4comX28seg LCD driver V2 MC141803 CE Power supply for Pads circuits (3.15v)
L L L Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z
TCP LCM YSCLK/LP signal output MC141803 RWTCP2 LCD module CE Bit2 of general purpose I/O port C UART2 serial input IR receive input TCP LCM YDU signal output Int. 4comX28seg LCD driver V1 MC141803 CSBit3 of general purpose I/O port C UART2 serial output IR transmit output Bit7 of general purpose I/O port F SEG19 of int. 4comX28seg LCD driver Bit7 of key scan circuit output Bit4 of general purpose I/O port C Bit6 of general purpose I/O port F SEG18 of int. 4comX28seg LCD driver Bit6 of key scan circuit output Bit5 of general purpose I/O port C
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ATJ2001 PDA+MP3 Decoder
Actions Semiconductor Co.,LTD 87 GIOF5 BI (1) 87 SEG17 O 87(2) KEYO5 O 88 88(1) 88(2) 89 90 90(1) 91 91(1) 91(2) 92 92(1) 92(2) 93 93(1) 93(2) 94 94(1) 94(2) 95 95(1) 96 96(1) 96(2) 97 97(1) 97(2) 98 98(1) 98(2) 99 99(1)
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Z Z Z Z Z Z
Bit5 of general purpose I/O port F SEG17 of int. 4comX28seg LCD driver Bit5 of key scan circuit output Bit4 of general purpose I/O port F SEG16 of int. 4comX28seg LCD driver Bit4 of key scan circuit output Power supply for Pads circuits (3.15v)
GIOF4 SEG16 KEYO4 VCC GIOG0 SEG20 GIOF3 SEG15 KEYO3 GIOF2 SEG14 KEYO2 GIOF1 SEG13 KEYO1 GIOF0 SEG12 KEYO0 GIOG1 SEG21 GIOE7 SEG11 KEYI11 GIOE6 SEG10 KEYI10 GIOE5 SEG9 KEYI9 GIOE4 SEG8
BI O O PWR BI O BI O O BI O O BI O O BI O O BI O BI O I BI O I BI O I BI O
Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z
Bit0 of general purpose I/O port G SEG20 of int. 4comX28seg LCD driver Bit3 of general purpose I/O port F SEG15 of int. 4comX28seg LCD driver Bit3 of key scan circuit output Bit2 of general purpose I/O port F SEG14 of int. 4comX28seg LCD driver Bit2 of key scan circuit output Bit1 of general purpose I/O port F SEG13 of int. 4comX28seg LCD driver Bit1 of key scan circuit output Bit0 of general purpose I/O port F SEG12 of int. 4comX28seg LCD driver Bit0 of key scan circuit output Bit1 of general purpose I/O port G SEG21 of int. 4comX28seg LCD driver Bit7 of general purpose I/O port E SEG11 of int. 4comX28seg LCD driver Bit11 of key scan circuit input Bit6 of general purpose I/O port E SEG10 of int. 4comX28seg LCD driver Bit10 of key scan circuit input Bit5 of general purpose I/O port E SEG9 of int. 4comX28seg LCD driver Bit9 of key scan circuit input Bit4 of general purpose I/O port E SEG8 of int. 4comX28seg LCD driver
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ATJ2001 PDA+MP3 Decoder
Actions Semiconductor Co.,LTD 99(2) KEYI8 I 100 100(1) 100(2) 101 101(1) 102 102(1) 102(2) 103 103(1) 103(2) 104 104(1) 104(2) 105 105(1) 105(2) 105(3) 106 106(1) 106(2) 106(3) 107 107(1) 108 108(1) 108(2) 108(3) 109 110 110(1) 110(2) 110(3) GIOE3 SEG7 KEYI7 GIOG2 SEG22 GIOE2 SEG6 KEYI6 GIOE1 SEG5 KEYI5 GIOE0 SEG4 KEYI4 GIOD7 SEG3 TCPD7 KEYI3 GIOD6 SEG2 TCPD6 KEYI2 GIOG3 SEG23 GIOD5 SEG1 TCPD5 KEYI1 GND GIOD4 SEG0 TCPD4 KEYI0
8
Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z / Z Z Z Z
Bit8 of key scan circuit input Bit3 of general purpose I/O port E SEG7 of int. 4comX28seg LCD driver Bit7 of key scan circuit input Bit2 of general purpose I/O port G SEG22 of int. 4comX28seg LCD driver Bit2 of general purpose I/O port E SEG6 of int. 4comX28seg LCD driver Bit6 of key scan circuit input Bit1 of general purpose I/O port E SEG5 of int. 4comX28seg LCD driver Bit5 of key scan circuit input Bit0 of general purpose I/O port E SEG4 of int. 4comX28seg LCD driver Bit4 of key scan circuit input Bit7 of general purpose I/O port D SEG3 of int. 4comX28seg LCD driver Bit7 of TCP data bus Bit3 of key scan circuit input Bit6 of general purpose I/O port D SEG2 of int. 4comX28seg LCD driver Bit6 of TCP data bus Bit2 of key scan circuit input Bit3 of general purpose I/O port G SEG23 of int. 4comX28seg LCD driver Bit5 of general purpose I/O port D SEG1 of int. 4comX28seg LCD driver Bit5 of TCP data bus Bit1 of key scan circuit input Digital signal ground Bit4 of general purpose I/O port D SEG0 of int. 4comX28seg LCD driver Bit4 of TCP data bus Bit0 of key scan circuit input
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BI O I BI O BI O I BI O I BI O I BI O O I BI O O I BI O BI O O I PWR BI O O I
ATJ2001 PDA+MP3 Decoder
Actions Semiconductor Co.,LTD 111 VDD PWR 112 112(1) 112(2) 112(3) 113 113(1) 113(2) 113(3) 114 114(1) 115 115(1) 115(2) 115(3) 116 116(1) 116(2) 116(3) 117 117(1) 118 118(1) 119 120 120(1) 121 122 123 124 125 126 126(1) 127
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Power supply for core (2.35v) Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z H H H H L Z Z L L L L L Z Z L Bit3 of general purpose I/O port D COM3 of int. 4comX28seg LCD driver Bit3 of TCP data bus Bit3 of TCP2 data bus Bit2 of general purpose I/O port D COM2 of int. 4comX28seg LCD driver Bit2 of TCP data bus Bit2 of TCP2 data bus Bit4 of general purpose I/O port G SEG24 of int. 4comX28seg LCD driver Bit1 of general purpose I/O port D COM1 of int. 4comX28seg LCD driver Bit1 of TCP data bus Bit1 of TCP2 data bus Bit0 of general purpose I/O port D COM0 of int. 4comX28seg LCD driver Bit0 of TCP data bus Bit0 of TCP2 data bus Ext. memory write active signal Nand type flash write enable Ext. memory read active signal Nand type flash read enable Bit0 of ext. memory address bus Bit5 of general purpose I/O port G SEG25 of int. 4comX28seg LCD driver Bit1 of ext. memory address bus Bit2 of ext. memory address bus Bit3 of ext. memory address bus Bit4 of ext. memory address bus Bit5 of ext. memory address bus Bit6 of general purpose I/O port G SEG26 of int. 4comX28seg LCD driver Bit6 of ext. memory address bus
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GIOD3 COM3 TCPD3 LCDD3 GIOD2 COM2 TCPD2 LCDD2 GIOG4 SEG24 GIOD1 COM1 TCPD1 LCDD1 GIOD0 COM0 TCPD0 LCDD0 MWRWEMRDRE A0 GIOG5 SEG25 A1 A2 A3 A4 A5 GIOG6 SEG26 A6
BI O O O BI O O O BI O BI O O O BI O O O BI O BI O BI BI O BI BI BI BI BI BI O BI
ATJ2001 PDA+MP3 Decoder
Actions Semiconductor Co.,LTD 128 A7 BI 129 130 131 131(1) 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 155(1) 156 157 157(1) A8 ENMIGIOG7 SEG27 GND VCC A9 A10 A11 SIRQA12 A13 STANDBYZICEDO ZICEDI ZICECK CE2TEST ZICERSTCE3ZICEENCE4RESETA14 CE5GND D0 GIOA0 CD0 D1 GIOA1 IOCS16BI SIU BI O PWR PWR BI BI BI SIU BI BI O O SIU SIU O SI SIU O SIU O SI O O PWR BI BI I BI BI I L L L H L L L L H H H L H H H H H L H / Z Z Z Z Z Z L L H Z Z / Bit7 of ext. memory address bus Bit8 of ext. memory address bus Ext. non-maskable interrupt input Bit7 of general purpose I/O port G SEG27 of int. 4comX28seg LCD driver Digital signal ground Power supply for Pads circuits (3.15v) Bit9 of ext. memory address bus Bit10 of ext. memory address bus Bit11 of ext. memory address bus Ext. maskable interrupt input Bit12 of ext. memory address bus Bit13 of ext. memory address bus System in standby mode output signal Debug pin, data output from DSU Debug pin, data input to DSU Debug pin, clock into DSU Ext. memory chip select 2 Test mode control, 0:normal mode 1:test mode Debug pin, to reset DSU Ext. memory chip select 3 Debug pin, to enable DSU Ext. memory chip select 4 System reset input Bit14 of ext. memory address bus Ext. memory chip select 5 Digital signal ground Bit0 of ext. memory data bus Bit0 of general purpose I/O port A IDE card detection Bit1 of ext. memory data bus Bit1 of general purpose I/O port A IDE 8 or 16 data bus indicate
10
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Actions Semiconductor Co.,LTD 158 D2 BI 159 159(1) 159(2) 160 161 162 162(1) 162(2) 163 164 165 166 167 167(1) 167(2) 168 169 170 170(1) 170(2) 171 172 173 173(1) 173(2) 174 175 175(1) 175(2) 176 GIOA2 CS1FX_SSD3 D4 GIOA3 IORDY FX_READYD5 A25 VCC D6 GIOA4 CS0FX_SCK D7 CE0GIOA5 IRQ FX_MOSI CE1CE6GIOA6 IOWFX_MOSO CE7GIOA7 IORFX_CKOUT1 VDD BI O O BI BI BI I I BI BI PWR BI BI O O BI O BI I I O O BI O O O BI O O PWR Z Z Z Z Z H Z Z Z H H Z Z Z H Z Z Z Z Z Z Z Z Z Z Z Z Z L Bit2 of ext. memory data bus Bit2 of general purpose I/O port A IDE chip select 1 Active low slave select of FLEX decoder Bit3 of ext. memory data bus Bit4 of ext. memory data bus Bit3 of general purpose I/O port A IDE IORDY FLEX decoder SPI packet ready Bit5 of ext. memory data bus Bit25 of ext. memory address bus Power supply for Pads circuits (3.15v) Bit6 of ext. memory data bus Bit4 of general purpose I/O port A IDE chip select 0 Message shift clock of FLEX decoder Bit7 of ext. memory data bus Ext. memory chip select 0 Bit5 of general purpose I/O port A IDE IRQ Message input from FLEX decoder Ext. memory chip select 1 Ext. memory chip select 6 Bit6 of general purpose I/O port A IDE IOWMessage output to FLEX decoder Ext. memory chip select 7 Bit7 of general purpose I/O port A IDE IORFLEX decoder clock (76.8KHz) Power supply for core (2.35v)
11
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Actions Semiconductor Co.,LTD Note: PWR : power A : analog pad AI : analog input AO : analog output Z : high resistant I : digital input O : digital output BI : bidirectional input/output SI : schmitt input SIU : schmitt input with int. pull-up resistant DSU: Developing Support Unit xxx(m) : multiplex pin's function m TCP: Tape Carrier Package , such as SEIKO EPSON LCD module TCP2: ASIC2/3 LCD module Note2: key in pads have int. pull-up resistants when key in mode enable. note3: Avoid AC'97 ATE TEST MODE AC'97_SYNC : output `L' after 3 system clocks, go "Z" AC'97_SDO : output `L' after 3 system clocks, go "Z" AC'97_RST- : output `L' after 3 system clocks, go "H"
12
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132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89
U? 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176
GND GIOG7 NMIA8 A7 A6 GIOG6 A5 A4 A3 A2 A1 GIOG5 A0 MRDMWRGIOD0 GIOD1 GIOG4 GIOD2 GIOD3 VDD GIOD4 GND GIOD5 GIOG3 GIOD6 GIOD7 GIOE0 GIOE1 GIOE2 GIOG2 GIOE3 GIOE4 GIOE5 GIOE6 GIOE7 GIOG1 GIOF0 GIOF1 GIOF2 GIOF3 GIOG0 VCC LOSCI LOSCO GND A15 AC97RSTA16 GIOB0 A17 GIOB1 A18 GIOB2 A19 GIOB3 A20 GIOB4 A21 GIOB5 A22 GIOB6 A23 A24 GIOB7 VCC USBDUSBD+ USBVBUS PVDD PAOR PAOL PGND PAIR PAIL AOUTR AOUTL VRDA VLAD VRAD AGIC MICOUT MICIN VMIC AGND Y2 Y1
VCC A9 A10 A11 SIRQA12 A13 STANDBYZICEDO ZICEDI ZICECK CE2TEST ZICERSTCE3ZICEENCE4RESETA14 CE5GND D0 GIOA0 D1 GIOA1 D2 GIOA2 D3 D4 GIOA3 D5 A25/IFIN VCC D6 GIOA4 D7 CE0GIOA5 CE1CE6GIOA6 CE7GIOA7 VDD
ATJ2001P176
GIOF4 GIOF5 GIOC5 GIOF6 GIOC4 GIOF7 GIOC3 YDU GIOC2 YSCLK/LP VCC FRAME VDD DISOFF GIOC1 XSCLK GIOC0 CKOUT2 GND HOSCO HOSCI AVSS AVDD DCOP1 DCOP3 DCOP2 VP2 VDD2 VP1 DCF1 DCF2 DCF3 VBAT DCDIS VL3 VL2 VL1 VL0 VREFI IBIAS SEL AVCC X2 X1
88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45
RA3930P176
13
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
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ELECTRICAL CHARACTERISTIC
A Absolute Maximum Ratings (TA = 25C) Parameter
Supply voltage Input voltage Storage temperature
Symbol
VDD VCC Vi Tstg
Condition
2.5V 3.3V VCC >= 3.3 VCC < 3.3
Rating
-0.5 to +3.0 -0.5 to +3.9 -0.5 to +3.9 -0.5 to VCC+0.6 -65 to +150
Unit
V V V V
Cautions 1. Do not short-circuit two or more output pins simultaneously. 2. If even one of the above parameters exceeds the absolute maximum ratings even momentarily, the quality of the product may be degraded. The absolute maximum ratings,therefore, specify the value exceeding which the product may be physically damaged. Use the product well within these ratings. The specifications and conditions shown in DC Characteristics and AC characteristics are the ranges for normal operation and quality assurance of the product.
B
Capacitance (TA = 25C, VCC = 0 V)
Parameter Symbol CI CIO Condition
fC = 1 MHz Unmeasured pins returned to 0 V
MIN.
MAX. 15 15
Unit pF pF
Input capacitance I/O capacitance
C
DC Characteristics (TA = -10 to +70C, VDD = 2.35 V, VCC = 3.15 V)
Symbol Condition MIN. TYP. MAX. Unit
Parameter
High-level output voltage Low-level output voltage High-level input voltage Low-level input voltage Input leakage current Output leakage current Supply Current Two batteries
VOH VOL VIH VIL ILI ILO
IOH = -2 mA IOL = 2 mA
2.4 0.4
0.6* VCC VCC + 0.6 0.4VC C
V V V V uA uA
-0.3 VCC = 3.6 V, VI = VCC, 0 V VCC = 3.6 V, VI = VCC, 0 V
10 5
In Fullspeed mode (MCU run 24.576MHz in internal SRAM,DSP run 36MIPS)
40
60
mA
14
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Actions Semiconductor Co.,LTD mode In Standby mode IVDD In Fullspeed mode (MCU run 24.576MHz in internal SRAM,DSP run 36MIPS) In Standby mode Ivcc
Notes 1.
50
150
200
uA
9
16
40
uA
9
18
40
uA
IvDD is a total power supply current for the 2.5 V power supply. IvDD is applied to the LOGIC and PLL and OSC block. Ivcc is a total power supply current for the 3.3 V power supply. Ivcc is applied to the USB, IO, TP, and AD block.
D
AC Characteristics (TA = -10 to +70C, VDD = 2 to 3 V, VCC = 2.7 to 3.6 V)
AC test input waveform VCC All input pins 0V
0.6VCC 0.4VCC
Test Points
0.6VCC 0.4VCC
AC test output measuring points VCC All output pins 0V
(1) Reset parameter
Parameter Reset input low-level width Symbol tWRSL Condition RESET# pin MIN. 160 MAX. Unit s
0.5VCC
Test Points
0.5VCC
VCC RESET# 0V
(2) Initialization parameter
Parameter Symbol Condition
tWRSL
MIN.
MAX.
Unit
15
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Data sampling time (from RESET# ) Output delay time (from RESET# ) tOD 61.04 s tSS 61.04 s
32.768KHz RESET# I/O PINs
Hi-Z
tSS tOD
Normal Operation Sampling Point
(3) GPIO interface parameter Parameter
Input level width GPIO input rise time GPIO input fall time Output level width
Symbol tGPIN tGPRISE tGPFALL tGPOUT
Condition
Normal operation 11/
MIN.
MAX.
200 200
Unit
s ns ns ns
fMCUclk
11/
fMCUclk
Notes 1. fMCUclk is the frequency that MCU is running upon.
(a) Input level width
(b) Input rise/fall time
(c) Output level width
16
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(4) Ordinary ROM parameter
Parameter
Data access time (from address) Data access time (from CEx# ) Data input setup time Data input hold time
Note Note
Symbol
tACC tCE tDS tDH
Condition
HOSC=24.576MHz HOSC=24.576MHz HOSC=24.576MHz HOSC=24.576MHz
MIN.
102 82 0 0
MAX.
Unit
ns ns ns ns
t ACC
A[24:0] CEn-/MRD-
t CE t DS t DH
D[7:0](I)
(5) External system bus parameter
Parameter
Address setup time (to command signal)
Note 1, 2
Symbol
tXAS tXAS
Condition
Memory Read Memory Write
MIN. MAX. Unit
0.5T 1.5T 0.5T 0 3 0 0 T 0.5T 2T ns ns ns ns ns ns ns
Address hold time (from command signal)Note 1, 2 Data output setup time (to command signal)
Note 1 Note 1
tXAH tWXDS tWXDH tRXDS tRXDH
Data output hold time (from command signal) Data input setup time (to command signal)
Note 1 Note 1
Data input hold time (from command signal)
Notes 1. MRD#, MWR# are called the command signals for the External System Bus Interface. 2. T (ns) = 1000 / fMCUCLK
17
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MCUCLK A[24:0] CEnMRDD[7:0](I) MWRD[7:0](O)
1 t XAS
2
3 t XAH
t RXDS
t RXDH
t XAS t WXDS
t XAH
t WXDH
Bus Operation
(a) Instruction fetch cycle
MCU CLK MRD# CEn#
(b) Memory read cycle
MCU CLK MRD# CEn#
(b) Memory write cycle
MCU CLK MWR# CEn#
18
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(6) Keyboard interface parameter
Parameter
KEYOUT (7:0) low-level width Voltage stabilization time (KEYOUT n KEYOUT (n+1)) Key scan interval time Key input delay time (from KEYOUT n) Key input hold time (from KEYOUT n) tKI tKS tKH
Symbol
tSCAN tKWAIT
Condition
Debounce time=2.5ms Debounce time=2.5ms Debounce time=2.5ms Debounce time=2.5ms Debounce time=2.5ms
MIN. MAX. Unit
130 0 s s
130 0 0
s s s
Remarks 1. KEYOUT(7:0) is multiplexed with GIOF(7:0); KEYIN(3:0) is multiplexed with GIOD(7:4); KEYIN(11:4) is multiplexed with GIOE(7:0) 2. Keyscan Debouncing time is set thru Bit(2:0) of the MFP Configuration1 Register[0xB1h] 3. n = 0 to 7
(a) Keyboard scan parameter 1
KEYOUTn
(output)
tKWAIT tSCAN
KEYOUT(n+1)
(output)
Remark n=0 to 6
(b) Keyboard scan parameter 2
0 KEYOUT (output) 1 KEYOUT (output)
ss ss ss
tKWAIT tKI
7 KEYOUT (output)
(c) Keyboard port parameter
19
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KEYOUTn
(output)
KEYIN(7:0)
(input)
tKS
tKH
Remark n=0 to 7
(7) S/PDIF interface parameter
X Channel A
Y Channel B
Z Channel A Sub-frame
Y Channel B Sub-frame
X Channel A
Y Channel B Frame 1
Frame 191
Frame 0 Start of Channel Status Block
Figure 7.1.
Frame/Block Format
1
0
0
0
1
1
101100110101
Figure 7.2. Biphase-Mark Encoding
Figure 7.3. Preamble Forms
Sub-f ram e
Pream ble
AuxData
Audio Data V alidity User Data Channel Status Data Parity Bit
MSB
bit
0
34
78
2728293031 VUCP
Figure 7.4.
LSB
Sub-frame Format
(8) Serial interface parameter
20
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Actions Semiconductor Co.,LTD 13 Prescale Value Baud Rate 600 1200 1800 2000 2400 3600 4800 7200 9600 14400 19200 28800 38400 57600 115200 230400 460800 750000 921600 1500000
Note : Data transfer rate per bit, which is determined by the divisor of the baud-rate generator that is set with UART1/2 Baud Rate Registers and clock prescaler that is set with UART1/2 Control Registers. (9) A/D Converter Characteristics (TA = -10 to +70C, VDD = 2.0 to 3.0 V, VCC = 2.7 to 3.6 V)
1.625 %Error 0.16% 0.16% 0.16% 0.53% 0.16% 0.16% 0.16% 0.16% 0.16% 0.16% 0.16% 0.16% 0.16% 0.16% 0.16% Divisor 256 192 128 96 64 48 32 24 16 8 4 2 1 %Error 0.16% 0.16% 0.16% 0.16% 0.16% 0.16% 0.16% 0.16% 0.16% 0.16% 0.16% 0.16% 0.16% Divisor 208 156 104 78 52 39 26 13 2 1
1 %Error 0.16% 0.16% 0.16% 0.16% 0.16% 0.16% 0.16% 0.16% 0.00% 0.00%
Divisor 192 96 64 58 48 32 24 16 12 8 6 4 3 2 1 -
Parameter
Zero-scale error Full-scale error Integral linearity error Differential linearity error Analog input voltage
Symbol
ZSE RSE INL DNL VIAN
Condition
MIN.
TYP.
4.0 5.0 3.0 3.0
MAX.
Unit
LSB LSB LSB LSB
-0.3
AVDD + 0.3
V
S/N Ratio
MAX
: 64dB 55dB
THD+N (MAX) :
(10) D/A Converter Characteristics (TA =-10 to +70C, VDD = 2.0 to 3.0 V, VCC = 2.7 to 3.6 V)
Parameter Integral linearity error Symbol INL Condition MIN. TYP. 3.0 MAX. Unit LSB
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Differential linearity error DNL 3.0 LSB
I2S interface parameter
Symbol
Parameter Clock Output Frequency
Pin Name BCKIN BCKIN, LRCIN BCKIN, DIN
Min. Typ. 651 10 10
Max.
Unit ns
Test Conditions 48 kHz/s Stereo 16 bit/s
t
SOCLK
t t
Wordstrobe Hold Time after
SOISS
t t
falling edge of clock Data Hold Time after falling edge of clock
SOCLK/2
ns ns
SOODC
SOCLK/2
S/N Ratio
MAX
: 90dB 78dB
THD+N (MAX) :
E. MCU/DSP Dissipation (Ivdd VS. Frequency) 1.) MCU Dissipation (Vbat=3.0V,DSP under reset, MCU runs in internal SRAM) Clock Source 32.768KHZ
22
Divisor factor /(1--1024)
Ivdd(Max) 350uA
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/1 /2 /4 /8 /16 24.576MHz /32 /64 /128 /256 /512 /1024 8.5mA 4.7mA 2.9mA 1.8mA 1.4mA 1.1mA 0.96mA 0.88mA 0.85mA 0.84mA 0.83mA
2.) DSP Dissipation (Vbat=3.0V,MCU in Debug mode) DSP Speed (MIPS) 6 12 24 36 48 60 F RECOMMENDED SOLDERING CONDITIONS Ivdd (Max) 11.7mA 18.8mA 30.7mA 43.2mA 55.9mA 67.2mA
The conditions listed below shall be met when soldering the ATJ2001. Table 4-1. Soldering Conditions for Surface-Mount Devices
Soldering Process Soldering Conditions Peak package's surface temperature: 235C Infrared ray reflow Reflow time: 30 seconds or less (210C or more) Maximum allowable number of reflow processes: 2 Exposure limit: 3 days Partial heating method
Note
(10 hours of pre-baking is required at 125C afterward).
Terminal temperature: 300C or less Heat time: 3 seconds or less (for one side of a device)
Note Maximum number of days during which the product can be stored at a temperature of 25C and a relative humidity of 65% or less after dry-pack package is opened. Caution Do not apply two or more different soldering methods to one chip (except for partial heating method for terminal sections).
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control 23 Tel 86-756-3392353 Fax 86-756-3392251
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must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
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LQFP176: plastic low profile quad flat package; 176 leads; body 24 x 24 x 1.4 mm SOT506-1
c
y X A 132 133 89 88 ZE
e E HE (A 3) wM bp pin 1 index 45 1 e bp D HD wM ZD B vM B 44 vM A detail X Lp L
A A2 A1
176
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.15 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D (1) 24.1 23.9 E (1) 24.1 23.9 e 0.5 HD HE L 1.0 Lp 0.75 0.45 v 0.12 w 0.08 y 0.08 ZD 1.43 1.08 ZE 1.43 1.08 7 0o
o
26.15 26.15 25.85 25.85
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT506-1 REFERENCES IEC 136E25 JEDEC MS-026 EIAJ EUROPEAN PROJECTION
ISSUE DATE 00-01-19 00-02-01
25
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